Constructing Reliable Super Dense Phase Change Memory under Write Disturbance

Phase Change Memory (PCM) has better scalability and smaller cell size comparing to DRAM. However, further scaling PCM cell in deep sub-micron regime results in significant thermal based write disturbance. Naively allocating large inter-cell space increases cell size from ideal 4F 2 to 12F 2. While a recent work mitigates write disturbance along word-lines through disturbance resilient data encoding, which can shrink PCM cell size from 12F 2 to 8F 2 , it is ineffective for write disturbance along bit-lines, which is more severe due to widely adopted µTrench structure in constructing PCM cell arrays. In this thesis, we propose SD-PCM, an architecture to achieve reliable write operations in Super Dense PCM. In particular, we focus on mitigating write disturbance along bit-lines such that we can construct super dense PCM chips with 4F 2 cell size, i.e., the minimal for diode-switch based PCM. Based on simple verification-n-correction (VnC), we propose LazyCorrection and PreRead to effectively reduce VnC overhead and minimize cascading verification during write. We further propose (n:m)-Alloc for achieving good tradeoff between VnC overhead minimization and memory capacity loss. Our experimental results show that, comparing to a write disturbance-free low density PCM, SD-PCM achieves 80% capacity improvement in cell arrays while incurring around 0-10% performance degradation when using different (n:m) allocators. Phase Change Memory (PCM) has recently emerged as a promising memory technology that supplements to traditional DRAM technology for future main memory systems. As modern applications increasingly demand for large amount of memory, it is important to construct highly scalable and dense main memory with low power consumption [23, 14]. Unfortunately, DRAM faces both scalability and power consumption challenges — the path to scale DRAM beyond 20nm is unclear, and the refresh power from DRAM chips of large capacity is significant [16]. PCM has better scalability and better cell size — PCM chips can be constructed with 20nm technology and diode-switch based PCM exhibits 4F 2 cell size [8]. As a non-volatile memory technology, PCM has no leakage power from the cell. In recent studies, PCM has been proposed to replace a significant portion of DRAM main memory for achieving the overall energy effectiveness [35, 23, 14]. A PCM cell takes advantage of phase change material (GST [24]) to record data. By the application of heat generated through electrical pulses, the phase change material inside each PCM cell can be melted (RESET) or crystallized (SET). Scaling PCM in …